1. Field of the Invention
The present invention relates generally to a method of forming a stacked capacitor of a dynamic random access memory (DRAM) cell, and more specifically to a method of forming a storage node (viz., charge storage electrode) of a stacked capacitor using an etch blocking film of silicon oxide.
2. Description of the Related Art
As is known in the art, it is a current practice to use a one-transistor dynamic memory cell because it is able to meet the demand for ever increasing packaging density. The one-transistor DRAM cell consists of one select (access) transistor and one storage capacitor. The select transistor has a gate that is controlled by a word line. When the word line is selected, the select transistor turns on and the charge stored on the capacitor is fed out onto a bit line and to a sense amplifier.
With increasing integration of semiconductor devices, a three-dimensional structure of capacitor cell for increasing the effective charge storage area has been proposed to ensure reliable operations of the DRAM. Generally, there are two types of three-dimensional capacitor structures, one of which is a stacked capacitor and the other is a trenched capacitor. However, It is a recent trend to prefer the stacked capacitor rather than the trenched one in that the stacked capacitor is less susceptible to a soft error problem due to alpha radiation emitted from the packaging material (for example).
By way of example, a cylinder type stacked capacitor is disclosed in Japanese Laid-open Patent Application Nos. 3-232271 and 6-29463. Further, another approach to increasing the capacitance is a fin type stacked capacitor that is disclosed in Japanese Laid-open Patent Application No. 1-270344. Still further, a multi-fin type stacked capacitor is disclosed in a paper entitled "3-dimensional stacked capacitor cell for 16M and 64M DRAMs), 593-595 pages, 1988 International Electron Devices Meeting. The present invention is applicable to all the above mentioned types.
Before turning to the present invention it is deemed preferable to briefly describe, with reference to FIGS. 1(A) and 1(B), a DRAM cell having a conventional cylinder type stacked capacitor.
As shown in FIG. 1(A), a field oxide 10 is selectively formed on a silicon substrate 12 using a conventional cell segregation technique such as an LOCOS (local oxidation of silicon) method. It is readily understood that if an n-channel select transistor is to be fabricated, the substrate 12 should be p-type, while if a p-channel select transistor is to be formed, the substrate 12 should be n-type.
A select transistor of a DRAM cell is well known in the art and thus, a brief description thereof will be given for the sake of simplifying the disclosure. After forming the field oxide 10, source/drain regions 14 and 16 are provided on the substrate 12, after which a gate electrode 18 is formed via a gate oxide layer (no numeral) on the substrate 12. These regions 14, 16 and 18 constitute the select transistor.
A word line 20 is formed on the field oxide 10 in a direction perpendicular to the drawing sheet. Although not shown in FIG. 1, the word line 20 is connected to the gate electrode 18. Subsequently, an interlayer dielectric film (silicon oxide) 22 is deposited in a manner to cover the gate electrode 18 and the word line 20. More specifically, the interlayer dielectric film 22 consists of two layers formed using a CVD (chemical vapor deposition) process, one of which is an HTO (high temperature oxide) layer and the other is a BPSG (boro-phospho-silicate glass) layer deposited on the former one. The dielectric film 22 is then subjected to annealing at a temperature between 750 and 900.degree. C. so as to improve flatness by reflow.
Following this, a contact hole 24 is formed or cut on the source/drain region 14 and is filled with an electrically conductive material such as tungusten, titanium nitride, tungsten silicide, etc. Thus, a bit line contact plug 26 is formed. Thereafter, the top surface of the insulator layer 22 is patterned, using a photolithography technique, so as to form a bit line 28 (denoted by dashed lines). Another interlayer dielectric film 30 is then deposited on the interlayer dielectric film 22 in a manner to cover the bit line 26, after which the dielectric film 30 is flattened using a chemical mechanical polishing (CMP) technique.
A silicon nitride film 32, which functions as an etch blocking film (or stopper), is formed on the dielectric film 30 by way of a photolithography process. Thereafter, a contact hole 34 is formed on the source/drain region 16. Although not clearly shown in FIG. 1(A), an amorphous silicon film including phosphorous with density of 1.5.times.10.sup.20 atoms/cm.sup.2 is deposited on the top surface of the silicon nitride film where the contact hole 34 is open. This film deposition is done using a LPCVD (low pressure chemical deposition) method using gases of PH.sub.3 and SiH.sub.4 (or Si.sub.2 H.sub.6).
Subsequent series of process steps involve the formation of a lower charge storage electrode (viz., storage node) 35, a sidewall 36, and an electrode shaping film 37. These steps are not described in detail at this stage for the sake of simplifying the disclosure but will be made clearer as the description proceed to FIGS. 2(C)-2(H). Following this, the substrate 10 is immersed in a hydrofluoric acid solution in order to remove, by etching, the electrode shaping film 37, as shown in FIG. 1(B). A reference numeral 38 indicates a storage node (viz., lower charge storage electrode) of a DRAM cell, which consists of the electrode 35 and the sidewall 36.
In the above, the silicon nitride film 32 is an etch blocking (stopping) film which is used to remove the electrode shaping film 37. That is, the silicon nitride film 32 is provided to protect the interlayer dielectric film 30 from being etched. However, it is not seldom that a comparatively large stress of the silicon nitride film 32 causes cracks in the layer 32 itself and the interlayer dielectric film 30. Further, the silicon nitride film 32 tends to exhibit charge-up (accumulation of charges) due to a high electrical trap density thereof which is inherent in silicon nitride. In addition, the silicon nitride film 32 has characteristics of preventing a hydrogen gas to pass therethrough, which causes a problem of insufficient annealing by the hydrogen gas. The above mentioned difficulties lead to the lowering of memory cell operation reliability as well as yield reduction of DRAMs.